Analysis and Design of a 970-MHz, 108-Stage CMOS Ambient RF Energy Harvester With −36.5-dBm Input Power Sensitivity

Analysis and Design of a 970-MHz, 108-Stage CMOS Ambient RF Energy Harvester With −36.5-dBm Input Power Sensitivity

clock Volume: 72, Issue: 6, June 2024

authorYoomi Park

Analysis and Design of a 970-MHz, 108-Stage CMOS Ambient RF Energy Harvester With −36.5-dBm Input Power Sensitivity

Abstract
DOI: 10.1109/TMTT.2023.3331326   IEEEXplore: https://ieeexplore.ieee.org/document/10321827
Device
28-nm CMOS ambient RF energy harvester based on the Dickson architecture with 108 stages.
Spectrum
970 MHz
Novelty
On-off power management technique enhances input power sensitivity. A novel optimization strategy determines that a 1 / 0.09 rectifier cell channel width / length (W/L) and N=108 stages optimizes performance.
Application
Powering sensor nodes in wireless sensor networks.
Performance
-36.5 dBm input power sensitivity for 1.0 Vdc. 8.5 s charging time from 0.08 V to 1.0 V, 3.9 s from 0.89 V to 1.0 V with a 1 nF storage capacitor. 0.25% energy conversion efficiency (ECE) at -30.3 dBm RF input power.