DOI: 10.1109/TMTT.2026.3655408   IEEEXplore: https://ieeexplore.ieee.org/document/11365593

A scalable, planar, λ/2-spaced phased-array in 0.13-µm SiGe BiCMOS technology.

220 GHz

The design incorporates an image rejection subharmonic mixer (IRSHM) and a vector modulator (VM) with a reuse technique to minimize power consumption and occupied area. This architecture simultaneously enables image rejection, subharmonic up-conversion, and intermediate frequency (IF) phase and amplitude control. The phased-array chip employs a splicing architecture with a 2 × 2 array and on-chip antenna, where a ninth harmonic generator, a local oscillator (LO) signal distribution network, and four transmitters (TXs) are integrated.

High data rate wireless communication links for AI and vehicular applications, inverse synthetic aperture radar (ISAR) imaging.

RF bandwidth of 212–224 GHz; 36 dBm peak EIRP at 221 GHz with about 2 dBm output power per channel. 3-dB beam widths of 10° (horizontal) and 17° (vertical), with beam steering capabilities of ±60° and ±40° in the respective planes. Using a 32-element phase array and a 40-dBi dish antenna demonstrated, data rates of 4 Gbps (QPSK) and 6 Gbps (16-QAM) with corresponding error vector magnitude (EVM) values of 9.5% and 9.2%, respectively.