This article reviews low-jitter, fractional-N phase-locked loop (PLL) design approaches for local oscillators (LOs) with state-of-the-art phase noise and spurious tone performance for advanced wireless CMOS transceivers. The article begins with an overview of the digital-to-time converter (DTC)-assisted PLL architecture with lower jitter and better figure of merits (FoMs) compared to other PLL topologies. A design example illustrates considerations for ultra-low phase noise performance. Digital calibration techniques are explored for gain and nonlinearity calibration and range reduction. Finally, refined LO design examples are presented for a 5G FR2 cellular transceiver and a tri-band Wi-Fi 7 transceiver supporting 4K-QAM.