DOI: 10.1109/TMTT.2026.3719676   IEEEXplore: https://ieeexplore.ieee.org/document/11663151    

16-element phased-array transceiver (TRX) incorporating the on-chip up-/down-conversion paths and multiplier chain in a 40-nm CMOS process.

91.4 – 95.5 GHz (W-band)

A coupled-line (CL)-based transmit/receive (T/R) switch achieves under 1-dB insertion loss (IL) and improved TX/RX isolation with a minimum footprint. A low-loss 7-bit phase shifter (PS) topology with a hybrid PS and attenuator (PSATT) integrated into the interstage matching networks improves linearity constraints on cascaded active stages. Built-in calibration suppresses system-level local oscillator feedthrough (LOFT) and enhances the image rejection ratio (IRR).

Scalable next-generation W-band phased-array systems.

33 dBm peak TX conversion gain (CG) with 4.4-GHz 3-dB bandwidth, 12.6 dBm saturated output power (Psat). 22 dB RX conversion gain (CG), 9.7 dB noise figure (NF), and -28 dBm input 1-dB compression point (IP1dB). 15.5 dB gain tuning in 0.5-dB steps; 2.8° phase resolution. >26 dBc LOFT suppression and > 40 dBc IRR with the calibration system.