DOI: 10.1109/TMTT.2026.3712400   IEEEXplore: https://ieeexplore.ieee.org/document/11631645

2-D phased-array transceiver module with an aperiodic subarray configuration in fan-out wafer-level packaging (FOWLP) in 28 nm bulk CMOS.

139 - 143 GHz (D-band)

The transceiver module architecture consists of four 4-channel transceiver RFICs and 108 dual port silicon-based resonator antennas (SRAs) into a single module using fan-out wafer-level packaging (FOWLP) technology, serving both TX and RX operations in an 11x12 array with space allocated to the transceiver chips. 2D beamforming is achieved by grouping the uniform SRAs into 24 aperiodic subarrays based on the rule that a column or row cut of the SRA array follows the Beaty-based sequence to suppress grating lobes. A defect ground structure (DGS) is utilized for impedance matching in the chip-to-package transition with a slot structure to match the impedance with the microstrip line on the redistribution layer (RDL).

D-band transceivers with integrated beamforming.

20 dBm TX peak EIRP; 9.7 - 13.5 dB RX NF from 139 - 143 GHz. ±10° TX and RX effective 2D beamforming in both X and Y planes. Over the air (OTA) 32 and 20 Gb/s data rates were achieved for the TX and RX modes, respectively, using 16-QAM modulation at link distances of 60 and 8 cm with a bit error rate (BER) of approximately 10−3.