Kishan Joshi

Kishan Joshi  received his M.S. & Ph.D. degrees in electrical engineering from Arizona State University, Tempe, AZ, USA in 2016 & 2020 respectively. Since 2021, he is with Intel Corporation, Santa Clara, CA where he is involved in the design of fully integrated voltage regulators. From 2019 to 2021, he was with the Linear Power group in Texas Instruments, Tucson, AZ where he was involved in the design of linear low-dropout regulators. He was an analog design intern at Kilby Labs, Texas Instruments, Santa Clara, CA in 2016, at NXP Semiconductors, Chandler, AZ in 2017 and at Linear power group, Texas Instruments, Tucson, AZ in 2018 where he worked on power converters, analog-to-digital converters and ultra-low Iq LDOs respectively. From 2012 to 2014 he was a Digital Circuit Designer at Sankalp Semiconductors Pvt. Ltd., India where he worked on standard cell library design for mixed-signal libraries. His current research interests include low-power analog design, supply ripple rejection and power management IC design. He is a peer reviewer for IEEE TCAS-I & II, TPEL, APEC, ISCAS, Access. Since 2022 he has been serving as the Chair of San Francisco Bay Area Council PELS Chapter. He is also a member of the PELS TC-10 on design methodologies and the liaison to the EMC society.