DOI: 10.1109/TMTT.2025.3550168   IEEEXplore: https://ieeexplore.ieee.org/document/10938660

A planar-packaged terahertz (THz) transmitter with a highly integrated active chip in 40 nm CMOS technology and a folded reflectarray (FRA).

335 GHz

The CMOS chip incorporates a four-stage ring oscillator and a differential on-chip patch antenna that enables direct harmonic radiation without an impedance matching network. The four-stage ring oscillator with a gate-loaded varactor configuration broadens the frequency tuning range. The utilization of 1-bit phase quantization in the reflectarray allows for standard PCB techniques in the manufacturing process and addresses the trade-off between phase range and fabrication tolerance.

Advanced high-resolution imaging, high-speed wireless communication, remote sensing, and non-destructive detection.

12.3 dBm EIRP, 22 dB EIRP enhancement, 34.2% DC-to-EIRP efficiency; 7.1% relative bandwidth (tunable from 315 to 337.5 GHz); 49.6 mW DC power consumption.