DOI: 10.1109/TMTT.2025.3537588   IEEEXplore: https://ieeexplore.ieee.org/document/10879347    

Design methodology for mm-Wave low noise amplifiers in 65-nm CMOS to optimize for power consumption, gain and/or noise figure performance.

28 GHz

Multi-objective optimization algorithms, consideration for process, voltage and temperature (PVT) variations, machine learning (ML) based inductor design tools in lieu of EM simulation, and a placement and routing optimized automated layout generation tool combine for a robust and effective design methodology for mm-wave low noise amplifiers. Using this design methodology achieves performance improvements of more than 50% in power consumption and figure of merit compared to alternative design approaches.

5G/6G applications

2.26 mW at 0.6 VDD, 8.4 GHz bandwidth (BW, 22.3-30.7 GHz), 10 dB peak gain, – 8.7 dBm input 1-dB compression point (IP1dB), 3.8 dB noise figure (NF) at 28 GHz for LNA1 optimized for low power consumption. 4.8 mW at 0.6 VDD, 7.3 GHz bandwidth (BW, 22.3-29.6 GHz), 13.9 dB peak gain, – 11.74 dBm input 1-dB compression point (IP1dB), 3.47 dB noise figure (NF) at 28 GHz for LNA2 optimized for high gain and low noise figure.