Rick Sturdivant

Rick Sturdivant

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Biography

Rick Sturdivant received the Ph.D., from Colorado State University, M.S. from UCLA, and B.S. from California State University. He has worked in the aerospace industry and has founded several sucessful start up companies. He has taught engineering courses at Cal Poly Pomona and Azusa Pacific University. He is currently the founder and chief technology officer at MPT, Inc. Much of his research and product development has been in electronic packaging of phased arrays for radar, satellite, and communication applications.

He has published over 50 articles and conference papers. He is the author of the books Microwave and Millimeter-wave Electronic Packaging (Artech House, 2014) and co-author of Transmit Receive Modules for Radar and Communication Systems (Artech House, 2015), and RF and Microwave Microelectronic Packaging II (Springer Publishing, 2017).

He has been an invited speaker to IEEE chapters and international conferences. He was invited to give a professional development course at the 2017 EPTC Conference in Singapore on the topic of Electronic Packaging for 5G Microwave and Millimeter Wave Systems. He is a Senior Member of the IEEE.

Presentations

T/R MODULES USING 3D AND SIP PACKAGING

T/R modules have traditionally used metal housings with glassed-in interconnects and ceramic substrates. More recent approaches use 3D stacked substrates and the tile module approach. This approach resulted in lower cost, lower-profile and lighter-weight arrays. With advances in packaging materials and processes, System In a Package (SIP) approaches are being used for T/R modules. These approaches promise the realization of further cost reductions, large “membrane” arrays for space applications and improved array-level manufacturability. This presentation reviews traditional T/R module packaging, examines a tile module in detail, examines next generation T/R modules using SIP and array-level packaging approaches. The presentation concludes with a projection on future developments in phased arrays.

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