José Luis González-Jiménez

José Luis González-Jiménez is a Fellow and Research Director at CEA-Leti. He received the Diploma degree in telecommunication engineering from Ramon Llull University, Barcelona, Spain, in 1992, the M.Sc. degree in Telecommunications Engineering and the Ph.D. degree (Hons.) in electronic engineering from the Universitat Politecnica de Catalunya (UPC), Barcelona, in 1994 and 1998, respectively. He attained the “Habilitation à Diriger des Recherches – HDR” degree from Grenoble University, Grenoble, France, in 2013. From January to July 1999, he worked as a Guest Researcher with the University of Arizona, Tucson, AZ, USA, where he collaborated with Motorola on the design of high-speed digital-to- analog converters. From September 2007 to August 2008, he was a Visiting Researcher with the STMicroelectronics/CEA-Leti joint Advanced Research Laboratory, Minatec, Grenoble, where he was engaged in research on the design of millimeter-wave oscillators and substrate noise coupling in millimeter-wave CMOS integrated circuits (ICs). Until 2011, he was a full-time Associate Professor with the Department of Electronic Engineering, Universitat Politecnica de Catalunya, Barcelona. From 2015 to 2019, he was the Deputy Head of the RFIC Design Laboratory, CEA-Leti, Grenoble. He is also an Invited Lecturer at the Phelma Engineering School, Grenoble-Alpes University. He has been leading and participating in several international research projects and contracts with companies. He is the author of two books, three book chapters, more than 40 international journal articles, and more than 120 conference papers. He holds 23 patents. His research interests include very large-scale integration circuits and systems, mixed-signal/RF,  millimeter-wave and sub-THz ICs, silicon photonics, and signal and power integrity in SoC and RFICs. Dr. González-Jiménez was awarded a Fulbright Fellowship and regularly collaborates as a reviewer in journals, including IEEE Journal of Solid-State Circuits, IEEE Transactions of Circuits and Systems (I and II), IEEE Microwave and Wireless Components Letters, Electronics Letters, and IEEE Transactions on Microwave Theory and Techniques, and serves regularly for the technical program committee of several international conferences, including ISSCC, ESSERC, EuMW and IMS. From 2023 to 2025 he was the IEEE CAS society representative at the Steering Committee of the IEEE Future Networks Technical Community. He is a IEEE Senior Member and a EUMA Member.

This lecture will address innovative transceiver architectures for radio links aiming at very high throughput (100+ Gbp) and low energy consumption operating at D-band and subTHz frequencies. In the first place, channel aggregation architectures will be presented in detail. These architectures allow cover a large band at RF without imposing containing bandwidth requirement at the lower frequency interfaces, by combining multiple BB channels into parallel up and down conversion lanes. The design of the most critical building blocks will be addressed, as well as the packaging and module integration with the antennas, with experimental results from fabricated prototypes. Next, innovative techniques for the generation of the multiple LO signals required by these channel aggregation architecture will be presented and discussing, including efficient calibration methods. Finally, high gain antenna architectures will be covered, with a focus on alternatives to phased arrays for D-band and subTHz frequencies based on reconfigurable metasurfaces and transmit arrays. Overall, this lecture will follow the thread of minimizing the energy consumption of each component of the radio transceiver, from the baseband interfaces up to the antenna system. The lecture will conclude with some applicative examples where the performances of the links will be compared with the requirements of some use cases such as back/front haul links and smart factory networks.