Dan Jiao

Dan Jiao received the Ph.D. degree in electrical engineering from the University of Illinois at Urbana-Champaign, Urbana, IL, USA, in 2001. She then joined the Technology Computer-Aided Design (CAD) Division, Intel Corporation, until September 2005, where she was a Senior CAD Engineer, Staff Engineer, and Senior Staff Engineer. In September 2005, she joined Purdue University, West Lafayette, IN, USA, as an Assistant Professor with the School of Electrical and Computer Engineering. She is currently a Professor with Purdue University. She has authored 3 book chapters and over 300 papers in refereed journals and international conferences. Her current research interests include computational electromagnetics; high-frequency digital, analog, mixed-signal, and RF integrated circuit (IC) design and analysis; high-performance very large scale integration (VLSI) CAD; modeling of microscale and nanoscale circuits; applied electromagnetics; fast and high-capacity numerical methods; fast time-domain analysis, scattering and antenna analysis; RF, microwave, and millimeter-wave circuits; wireless communication; and bioelectromagnetics.

Dr. Jiao has served as a reviewer for many IEEE publications and conferences. She is an associate editor for the IEEE Transactions on Components, Packaging, and Manufacturing Technology. She was the recipient of the 2013 S. A. Schelkunoff Prize Paper Award of the IEEE Antennas and Propagation Society, which recognizes the Best Paper published in the IEEE Transactions on Antennas and Propagation during the previous year. She has been named a University Faculty Scholar by Purdue University since 2013. She was among the 85 engineers selected throughout the nation for the National Academy of Engineerings 2011 U.S. Frontiers of Engineering Symposium. She was the recipient of the 2010 Ruth and Joel Spira Outstanding Teaching Award, the 2008 National Science Foundation (NSF) CAREER Award, the 2006 Jack and Cathie Kozik Faculty Start Up Award (which recognizes an outstanding new faculty member of the School of Electrical and Computer Engineering, Purdue University), a 2006 Office of Naval Research (ONR) Award under the Young Investigator Program, the 2004 Best Paper Award presented at the Intel Corporation’s annual corporate-wide technology conference (Design and Test Technology Conference) for her work on generic broadband model of high-speed circuits, the 2003 Intel Corporation Logic Technology Development (LTD) Divisional Achievement Award, the Intel Corporation Technology CAD Divisional Achievement Award, the 2002 Intel Corporation Components Research Award, the Intel Hero Award (Intel-wide she was the tenth recipient), the Intel Corporation LTD Team Quality Award, and the 2000 Raj Mittra Outstanding Research Award presented by the University of Illinois at Urbana–Champaign.

The design of advanced integrated circuits and microsystems from zero to terahertz frequencies calls for fast and accurate electromagnetics-based modeling and simulation. The sheer complexity and high design cost associated with the integrated circuits and microsystems prevent one from designing them based on hand calculation, approximation, intuition, or trial and error. The move towards higher frequencies and heterogeneous technologies stresses the need even more.

However, the analysis and design of integrated circuits (ICs) and microsystems impose many unique challenges on electromagnetic analysis such as exponentially increased problem size and extremely multiscaled system spanning from nano- to centi-meter scales. These challenges become new driving forces of the advancement of Computational Electromagnetics (CEM) in recent years, since past techniques do not address them well.

CEM methods can be categorized into two broad classes: partial differential equation (PDE) and integral equation (IE) based solvers. In the past, fast solvers in both classes rely on iterative matrix solutions to solve large-scale problems. The optimal complexity of an iterative solver is O(N Nit Nrhs) with N being matrix size, Nit the number of iterations and Nrhs the number of right hand sides. In an IE solver, the underlying system matrix is dense. A dense matrix-vector multiplication in O(N) complexity represents an impressive complexity reduction as compared with conventional O(N2) techniques. This has been accomplished by past fast solvers. However, when the number of iterations and/or the number of right hand sides are large, which is true in IC problems, the complexity of fast iterative IE solvers is still high. In a PDE solver, the underlying system matrix is sparse, achieving a matrix-vector multiplication in O(N) complexity is straightforward. However, the number of iterations is large and the preconditioner cost is high when using existing iterative PDE solvers to analyze complicated IC problems. Moreover, the entire iteration must be repeated for each right hand side. This prevents the use of existing iterative solvers for analyzing realistic ICs in feasible run time.

In this talk, recent advances in fast direct solvers of O(N) (optimal) complexity will be presented, including both direct PDE and IE solvers, for addressing the ultra large problem size encountered in the IC design problems. In these solvers, the underlying dense or sparse system matrix is directly inverted or factorized in O(N) complexity. To show how these solvers work, a series of new accuracy controlled fast matrix arithmetic will be elaborated including the representation of a dense matrix of O(N2) elements using O(N) parameters with controlled accuracy, subsequent matrix-matrix multiplication, matrix factorization, and inversion performed in O(N) complexity with directly controlled accuracy. The application of these fast algorithms to the design and analysis of industry product-level integrated circuits and systems will be presented. Comparisons with direct and iterative solvers in the past will be made, which demonstrate the clear advantages of the new O(N) direct solvers.