2025 IEEE MTT-S Young Professionals Workshop on Modeling, Optimization, and Measurement Techniques for Active Devices (MOMA)

Co-chairs:
Gian Piero Gibiino (University of Bologna, Italy), Justin King (Trinity College Dublin, Ireland)

Abstract:
The fourth edition of this virtual workshop aims to highlight recent and emerging trends in the broad fields of modeling, optimization, and measurement techniques for active devices. Six presentations by Young Professionals (YPs) from industry and academia will cover topics ranging from SOI to GaN devices, device-level to circuit-level optimization, performance assessment, and related characterization challenges.

Event Date / Time:
November 6th,  2025
15:00 UTC to 18.30 UTC
16.00 CET to 19.30 CET
07:00 PST to 10.30 PST

This workshop will be conducted virtually via Zoom, and it is open to everyone free of charge upon registration. Please register here.

Workshop Agenda:

[Introduction] 15:00 UTC – 15:10 UTC

[Session 1] 15:10 UTC – 15:40 UTC

[S1-1] 15:10 – 15:40 UTC

Nijita Kesavan Namboothiri (pSemi, USA), “Unlocking RF Behavior in SOI MOSFETs: The Role of Body Connection”

Abstract – In silicon-on-insulator (SOI) MOSFETs, body configuration significantly influences RF performance. Floating body devices demonstrate enhanced cutoff frequency (ft), primarily due to reduced parasitic capacitance, but suffer from floating body effects such as impact ionization, which causes threshold voltage (Vt) shift and degrades linearity. In contrast, body-tied configurations mitigate these effects by connecting the body to the source via body tabs, at the cost of increased parasitic loading, layout area, and complexity. This work presents a comparative study of floating body and body-tied SOI MOSFETs, focusing on configurations with up to three body tabs. By means of a comprehensive RF characterization, we evaluate key RF metrics in both small and large signal conditions. The results reveal critical trade-offs between body contact geometry and RF performance, providing design insights for high-frequency SOI technologies.

[S1-2] 15:40 – 16:10 UTC

Rana ElKashlan (imec, Belgium), “Unlocking GaN Performance through Reliable On-Wafer Load Pull at FR3 and FR2”

Abstract – This talk will focus on practical techniques and considerations for on-wafer load pull characterization of GaN on Si HEMTs across FR3 and FR2 bands. Topics will include power budgeting strategies tailored to the target application, calibration validation techniques, and setup considerations for both low voltage (user equipment) and high voltage (infrastructure) measurements. The talk will also highlight how metrology-driven insights from load pull can directly support device and technology co-optimization.

[S1-3] 16:10 – 16:40 UTC 
 
Rafael Perez Martinez (Broadcom, USA), “Accelerating RF Device Modeling and Circuit Design via Derivative-Free Optimization”

Abstract – This presentation explores advanced derivative-free optimization (DFO) techniques for accelerating compact model parameter extraction for RF devices and circuit-level transistor sizing in RF designs. By replacing traditional manual tuning with a scalable, automated framework, the proposed approach efficiently extracts dozens of parameters with low fitting error and robustness to outliers, demonstrating its effectiveness in compact model parameter extraction. The talk also highlights the role of DFO in multi-objective optimization (MOO), enabling the rapid exploration of performance trade-offs and delivering Pareto-efficient, design-oriented solutions for applications such as power amplifier (PA) and low-noise amplifier (LNA) transistor sizing. Together, these approaches provide a faster, more reliable pathway from device modeling to optimized designs in next-generation RF systems.

[10-minute break]

[Session 2] 15:10 UTC – 16:55 UTC

[S2-1] 16:50 – 17:20 UTC

Fábio Passos, University of Lisbon, Portugal, , “AI/ML-Driven Hierarchical RF System Optimization with PVT and Yield Considerations”

Abstract – Traditional design methodologies for RF/mm-Wave ICs, while effective in many respects, are becoming increasingly inadequate in meeting the rapidly evolving demands of today’s high-performance, complex systems. In recent years, Artificial Intelligence (AI) and Machine Learning (ML) have been applied to RF/mm-Wave circuit design to enable automation. However, most existing approaches focus on relatively simple circuits, do not reach system level designs and often neglect critical aspects such as PVT robustness and yield—factors that are indispensable in modern nanometer technologies. This talk will explore how AI and ML techniques can be effectively leveraged and integrated into synthesis methodologies, automating the design process while explicitly targeting robust, yield-aware, and PVT-aware RF/mm-Wave circuits and how can systems be designed using an hierarchical approach.

[S2-2] 17:20 – 17:50 UTC 

Han Zhou (Chalmers University, Sweden), “Energy-Efficient Power Amplifier Architectures, Design Methodologies, and AI-Driven Inverse Synthesis Techniques”

Abstract – This presentation introduces innovative power amplifier (PA) architectures and design methodologies for energy-efficient 5G and 6G communication systems, as well as AI-driven inverse synthesis techniques. We present advanced PA architectures that enhance back-off efficiency, supported by theoretical insights and circuit-level demonstrations across multiple frequency bands and semiconductor technologies. Key trade-offs in the load modulation process of efficiency-enhancement PA architectures are analyzed to guide design decisions. Furthermore, we demonstrate how deep learning-based inverse synthesis techniques can assist in automating and accelerating the PA design flow, leading to improved performance and design-time reduction. This talk highlights the synergy between advanced PA theory and data-driven design strategies, offering practical benefits for next-generation communication systems.

[S2-3] 17:50 – 18:20 UTC

Dhecha Nopchinda (Gotmic, Sweden), “Measurement and Characterization of an E-Band Tunable Analog Predistorter”

Abstract – On the path to demonstrating Gotmic’s new generic tunable analog predistorter (APD) at E-band (71–86 GHz), several key challenges arose. The first was benchmarking: how should an APD be fairly compared with the ubiquitous digital predistorters (DPDs)? Can an APD on its own rival DPD performance, and what is the potential of combining the two? Secondly, coefficient extraction: while DPDs benefit from established direct and indirect learning methods, how should APD coefficients be identified and mapped onto the available control parameters? Finally, at the system level, what metrics best reflect user priorities, and how should a meaningful demonstration be designed? In this talk, I will present our approaches to these questions and share recent measurement results of Gotmic’s APD, first showcased at IMS2025 in San Francisco. I will highlight both the technical methodology and the system-level implications of introducing a tunable APD at millimeter-wave frequencies.

[10-min closing]